Industry Standard. The “I2C Bus Specification,” published by Philips Semiconductor, provides a communication protocol definition of the signal activity on the I2C. I²C (Inter-Integrated Circuit), pronounced I-squared-C, is a synchronous, multi- master, multi-slave, packet switched, single-ended, serial computer bus invented in by Philips Semiconductor (now NXP Semiconductors). Alternatively I²C is spelled I2C (pronounced I-two-C) or IIC (pronounced I-I-C). Since October Philips do define faster speeds: Fast mode, which is up to KHz and High . The I2C protocol provides a solution to this: the slave is allowed to hold the SCL.

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However, two masters may start transmission at about the same time; in this case, arbitration occurs. One might be dedicated to use with high-speed devices, for low-latency power management. It is illegal [4]: The master terminates a message with a STOP condition if this is the end of the transaction or it may send another START condition to retain control of the bus for another message a “combined format” transaction. From Wikipedia, the free encyclopedia.

If the master needs to communicate with other slaves it can generate a repeated start with another slave address without generation Stop condition.

Return 0 if ack protkcol the slave.

Such start byte is followed by an acknowledge pulse for interface compatibility reasons. Most SMBus operations involve single-byte commands. An addressed slave device may hold the clock line SCL low after receiving or sending a byte, indicating that it is not yet ready to process more data.

Note the bit rates are quoted for the transfers between master and slave without clock stretching or other hardware overhead. For each clock pulse one bit of data is transferred. Multi-master I2C can have more than one master and each can send commands. The master then waits for SCL to actually go high; this will be delayed by the finite rise time of the SCL signal the RC time constant of the pull-up resistor and the parasitic capacitance of the bus and may be additionally delayed by a slave’s clock stretching.

Communication With 7-bit I2C Addresses Each slave device on the bus should have a unique 7-bit address. The data transfer part protocol can cause trouble on the SMBus, since the data bytes are not preceded by a count, and more than 32 bytes can be transferred at once. In this situation, the master is in master transmit mode, and the slave is in slave receive mode.


If one transmitter sets SDA to 1 not driving a signal and a second transmitter sets it to 0 pull to groundthe result is that the line is low. After the Start condition the bus is considered as busy and can be used by another master only after a Stop condition is detected.

Microcontrollers that have dedicated I2C hardware can easily detect bus changes and behave also as I2C slave devices.

After this procedure the data can be read from the slave device.

The master device must either generate Stop or Repeated Start condition. The arbitration procedure can continue until all the data is transferred. The address and the data bytes are sent most significant bit first. Retrieved from ” https: If this bit is 0 then the master will write to the slave device. Seven bits is too few to prevent address collisions between the many thousands of available devices.

Archived PDF from the original on Archived from the original PDF on Two groups of 8 I2C addresses are reserved for future uses and one address is used for bit I2C addressing.

The bus has two roles for nodes: Each message is a read or a write. If the slave exists on the bus then it will respond with an ACK bit active low for acknowledged for that address.

I2C Bus Specification

Start symbols after the first, which begin a message but not a transaction, are referred to as repeated start symbols. The first transmitter then observes that the level of the line is different from that expected and concludes that another node is transmitting. SMBus is restricted to nine of those structures, such as read word N and write word Ninvolving a single slave. If microcontroller has I2C hardware and the microcontroller acts as a slave then the software needs to do nothing to check the bus state.

After the slave address and the data direction is sent, the master can continue with reading or writing.

Once the clock is released the master can proceed with the next byte. A bus means specification for the connections, protocol, formats, addresses and procedures that define the rules on the bus. Sometimes the master needs to write some data and then read from the slave device. Analog switches maintain the bidirectional nature of the lines but do not isolate the capacitance of one segment from another or provide buffering capability.


Master I2C device that has lost arbitration can generate SCL pulses until the byte ends and must then release the bus and go into slave mode. They are connected via resistors to a positive power supply voltage.

When used on SDA, this is called arbitration and ensures that there is only one transmitter at a time. When writing multiple bytes, all the bytes must be in the same byte page. In other projects Wikimedia Commons. Clock Synchronization and Handshaking Slave devices that need some time to process received byte or are not ready yet to send the next byte, can pull the clock low to signal to the master that it should wait. Synchronization Each master must generate its own clock signal and the data can change only when the clock is low.

Arbitration A process to determine which of the masters on the bus can use it when more masters need to use the bus.

I2C Bus Specification

In practice, most slaves adopt request-response control models, where one or more bytes following a write command are treated as a command or address. Main menu Skip to primary content. Similarly, the clock is in the high state until the first master pulls it low. Logic analyzers are tools that collect, analyze, decode, and store signals, so people can view the high-speed waveforms at their leisure.

Specification – I2C Bus

To simplify detection of I2C commands on the bus in such cases, a special I2C address called Start byte is used. To minimize the possible damage due to plugging 0. These speeds are more widely used on embedded systems than on PCs.